The invention relates to an integrated logic circuit having a first subcircuit which is connected between a first power supply line and an output of the circuit, and a second subcircuit which is connected between the output and a second power supply line, a current path of an additional transistor being connected at least between one of the subcircuits and the output in order to limit detrimentally high electrical fields in parts of one subcircuit, and a control electrode of the additional transistor being coupled only to the power supply line whereto the other subcircuit is connected.
A logic circuit of this kind is known from Netherlands Patent Application 8400523.
As the dimensions of transistors and other components of an integrated circuit become increasingly smaller, distances across which the full difference between the supply voltages is present also become increasingly smaller, resulting in high electrical field strengths. Such high field strengths, occurring notably in logic circuits in which the full power supply voltage is liable to occur across a single transistor, give rise to so-called hot-carrier stress and hot-carrier degradation effects in, for example field effect transistors. The high-energy free charge carriers accelerated by these fields collide with the crystal lattice of the substrate, thus releasing other charge carriers and causing substantial, unintended currents. The charge carriers dispersed to the interface between the substrate and the oxide due to the collisions will pass this interface when the energy is sufficiently high, so that they are intercepted by the oxide in which they cause an increased oxide load. Consequently, the switching characteristic of the transistor changes. The high field strengths in the transistor can also cause avalanche breakdown in a non-conductive pn-junction. As the dimensions of the transistor become smaller, the voltage across the pn junction at which this phenomenon occurs will be lower. In order to avoid such effects, in known logic circuits the current path of an additional transistor is included in a path between the output of the circuit and one of the power supply lines, a control electrode being connected to the other power supply line. The maximum voltage then occurring across the protected subcircuit is then reduced by a threshold voltage. However, the reduction of the dimensions of the parts of an integrated circuit also gives rise to another kind of problem. The switching occurring when the state of the logic circuit changes will cause induction voltages on the respective power supply lines, because these power supply lines have a substantial inductance. A pulse-shaped induction voltage pulse on one power supply line is transferred to the other power supply line via a capacitive coupling. The control electrode of the additional transistor in the known logic circuit will also receive this voltage pulse. A voltage pulse generated by a charging or discharging current is liable to circulate through a circuit loop which comprises, for example a part of one power supply line, the capacitive coupling, a part of the other power supply line and the control electrode of the additional transistor, giving rise to positive feedback which influences the charging or discharging current. Consequently, the output voltage of the logic circuit is liable to reach a stable value only after a delay; alternatively, instabilities may occur which cause increasingly larger current peaks. In a worst case situation such instabilities (oscillations) can damage the circuit.